reliability report for MAX17428GTJ+ plastic encapsulated devices june 11, 2009 maxim integrated products 120 san gabriel dr. sunnyvale, ca 94086 MAX17428GTJ+ approved by ken wendel quality assurance director, reliability engineering maxim integrated products. all rights reserved. page 1/5 downloaded from: http:///
conclusion MAX17428GTJ+ the MAX17428GTJ+ successfully meets the quality and reliability standards required of all maxim products. in additi on, maxim"s continuous reliability monitoring program ensures that all outgoing product will continue to meet maxim"s quality and reliabili ty standards. table of contents i. ........device description v. ........quality assurance information ii. ........manufacturing information vi. .......reliability evaluation iii. .......packaging information iv. .......die information .....attachments i. device description a. general the max17428 is a 1-phase quick-pwm? step-downvid power-supply controller for intel notebook cpus. the quick- pwm control provid es instantaneous response to fast load current steps. active voltage positioning reduces power dissipation and b ulk output capacit ance requirements and allows ideal positioning compensation for tantalum, polymer, or ceramic bulk output capacitors. the max17428 is intended for tw o different notebook cpu/gpu core applications: either bucking down the battery directly to create the core voltage, or else bucking down th e +5v sy stem supply. the single-stage conversion method allows this device to directly step down high-voltage batteries for the highest pos sible efficie ncy. alternatively, 2-stage conversion (stepping down the +5v system supply instead of the battery) at higher switching frequency provid es the minimum poss ible physical size. a slew-rate controller allows controlled transitions between vid codes. a thermistor-based temper ature sensor provides programmab le thermal protection. a current monitor provides an analog output current proportional to the processor load current. the max 17428 implem ents both the intel imvp-6.5 cpu core specifications (v3p3 = 3.3v), as well as the intel gmch graphics core specifications (v3p3 =gnd). the 17028 i s available in a 32-pin, 5mm x 5mm, tqfn package. maxim integrated products. all rights reserved. page 2/5 downloaded from: http:///
ii. manufacturing information a. description/function: 1-phase quick-pwm intel imvp-6.5/gmch contr oller b. process: s4 c. number of device transistors: 10146 d. fabrication location: texas e. assembly location: asat china, utl thailand f. date of initial production: 2008 iii. packaging information a. package type: 32-pin tqfn 5x5 b. lead frame: copper c. lead finish: 100% matte tin d. die attach: conductive epoxy e. bondwire: gold (1.0 mil dia.) f. mold material: epoxy with silica filler g. assembly diagram: #05-9000-2634 h. flammability rating: class ul94-v0 MAX17428GTJ+ i. classification of moisture sensitivity per jedec standard j-std-020-c level 1 j. single layer theta ja: 47c/w k. single layer theta jc: 1.7c/w l. multi layer theta ja: 29c/w m. multi layer theta jc: 2.7c/w iv. die information a. dimensions: 77 x 73 mils b. passivation: si 3 n 4 /sio 2 (silicon nitride/ silicon dioxide c. interconnect: aluminum/0.5% cu d. backside metallization: none e. minimum metal width: metal1 = 0.5 / metal2 = 0.6 / metal3 = 0.6 microns (as drawn) f. minimum metal spacing: metal1 = 0.45 / metal2 = 0.5 / metal3 = 0.6 microns (as drawn) g. bondpad dimensions: 5 mil. sq. h. isolation dielectric: sio 2 i. die separation method: wafer saw maxim integrated products. all rights reserved. page 3/5 downloaded from: http:///
v. quality assurance information a. quality assurance contacts: ken wendel (director, reliability engineering) bryan preeshl (managing director of qa) b. outgoing inspection level: 0.1% for all electrical parameters guaranteed by the datasheet. 0.1% for all visual defects. c. observed outgoing defect rate: < 50 ppm d. sampling plan: mil-std-105d vi. reliability evaluation a. accelerated life test MAX17428GTJ+ the results of the 135c biased (static) life test are pending. using these results, the failure rate ( ) is calculated as follows: = 1 = 1.83 (chi square value for mttf upper limit) mttf 192 x 4340 x 96 x 2 (where 4340 = temperature acceleration factor assuming an activation energy of 0.8ev) = 11.2 x 10 -9 = 11.2 f.i.t. (60% confidence level @ 25c) the following failure rate represents data collected from maxims reliability monitor program. maxim performs quarterly 1000 hour life test monitors on its processes. this data is published in the product reliability report found at http://www.ma xim- ic.com/. current monitor data for the s4 process results in a fit rate of 4.6 @ 25c and 79.2 @ 55c (0.8 ev, 60% ucl) b. moisture resistance tests the industry standard 85c/85%rh or hast testing is monitored per device process once a quarter. c. e.s.d. and latch-up testing the pe11-2 die type has been found to have all pins able to withstand a hbm transient pulse of +/-1000v per jedec jesd22-a114. latch-up testing has shown that this device withstands a current of +/-250ma, 1.5x vc cmax overvoltage per jesd78. maxim integrated products. all rights reserved. page 4/5 downloaded from: http:///
table 1 reliability evaluation test results MAX17428GTJ+ MAX17428GTJ+ test item test condition failure identification sample size number of failures static life test (note 1) ta = 135c biased time = 192 hrs. dc parameters & functionality 96 0 moisture testing (note 2) 85/85 ta = 85c rh = 85% biased time = 1000hrs. dc parameters & functionality 77 0 mechanical stress (note 2) temperature cycle -65c/150c 1000 cycles method 1010 dc parameters & functionality 77 0 note 1: life test data may represent plastic dip qualification lots. note 2: generic package/process data maxim integrated products. all rights reserved. page 5/5 downloaded from: http:///
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